This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-185284, filed Jun. 19, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit (IC) device and semiconductor device system and, more particularly to a synchronous semiconductor IC device and semiconductor device system.
2. Description of the Related Art
Presently, there has been widely used such a semiconductor memory for inputting/outputting data in synchronization with an external clock signal as synchronous DRAM (SDRAM), a double data-rate synchronous DRAM (DDR-SDRAM) and a ram-bus DRAM (RDRAM).
Of these, a DDR-SDRAM use an external reference potential VREF to decide a HIGH/LOW logical level of an external pin such as a data external pin.
FIG. 1 is a block diagram for outlining a semiconductor device system in which such a synchronous semiconductor memory is incorporated and FIG. 2, an expanded view for showing a frame A surrounded by a broken line in FIG, 1.
As shown in FIG. 1, on a wiring board are arranged as external wiring lines an external signal line (DQ) through which are propagated external signals (external input signal DIN and external output signal DOUT in this specification), an external reference potential line (VREF) to which is applied the external reference potential used in decision of the logical level of the external input signal DIN, an external input control clock signal line (CLOCK1) through which is propagated an external input control clock signal CLOCK1, and an external output control clock signal line (CLOCK2) through which is propagated another external output control clock signal CLOCK2. To the wiring board 101 is electrically connected a synchronous semiconductor memory 102.
The synchronous semiconductor memory 102 is provided with external pins 103, to which the wiring lines arranged on the wiring board 101 are connected. These external pins 103 are electrically connected via a pad 104 to internal wiring lines arranged in the synchronous semiconductor memory 102. In the example shown in FIGS. 1 and 2, those wiring lines connected to the external wiring lines include an internal reference potential line (Vref) electrically connected to the external reference potential line (VREF), an internal input control clock signal line (clock1) electrically connected to the external input control clock signal line (CLOCK1), and an internal output control clock signal line (clock2) electrically connected to the external output control clock signal line (CLOCK2).
Next, the following will describe operations of these lines.
 less than Operations When Inputting Signal greater than 
The signal is input in synchronization with at least one of leading and trailing edges of the internal input control clock signal clock1 synchronized with the external input control clock signal CLOCK1.
Specifically, an input circuit 105 receives an external input signal DIN through the pad 104 as an internal input signal Din. Then, it decides the logical level of this internal input signal Din against the internal reference potential Vref.
The logical level is specifically decided by an input receiver (IN.R.) 106 of the input circuit 102. The input receiver 106 compares, for example, the potential of the internal input signal Din to that of the internal reference potential Vref. If the potential of the internal input signal Din is lower than the internal reference potential Vref, it decides that the logical level is xe2x80x9cLOWxe2x80x9d and, if it is lower than that, decides that the logical level is xe2x80x9cHIGHxe2x80x9d.
The input receiver 106 is controlled by an input receiver control circuit (IN.C.) 107. The input receiver control circuit 107 generates an input control signal synchronized with this internal input control clock signal clock1 based on the internal input control clock 1 synchronized with the external input control clock signal CLOCK1. The input receiver 106 takes in the internal input signal Din in response to the input control signal to then output this internal input signal Din to the inside of the synchronous semiconductor memory 102.
 less than Operations When Outputting Signal greater than 
As in the case of signal inputting, the signal is output in synchronization with at least the leading and trailing edges of the internal output control clock clock2 synchronized with the external output control clock CLOCK2.
Specifically, an output circuit 108 is comprised of an output driver (OUT.D.) 109 and an output driver control circuit (OUT.C.) 110. An internal output signal Dout output from the inside of the synchronous semiconductor memory 102 is input to the output driver 109.
The output driver 109 is controlled by the output driver control circuit (OUT.C.) 110. The output receiver control circuit 110 generates an output control signal synchronized with the internal output control clock signal clock2 based on the internal output control clock signal clock2 synchronized with the external output control clock signal CLOCK2. The output driver 109 outputs the internal output signal Dout in synchronization with the output control signal to thereby drive the external signal line DQ via the pad 104 and the external pins 103. Thus, an external output signal DOUT is propagated to the external signal line DQ.
It is here assumed that noise occurred in such a synchronous semiconductor memory 102 and had an influence on the internal input control clock signal clock1, the internal output control clock signal clock2, and the internal reference potential Vref. In this case, the following situation is expected.
 less than When Internal Input Control Clock Signal Clock1 is Affected by Noise greater than 
As shown in FIGS. 3A and 3B, if the internal input control clock signal clock1 is affected by noise, for example, it is shifted in phase with respect to the external input control clock signal CLOCK1. This causes in turn the timing for taking in a signal by the input circuit 105 to be shifted from the edge of the external input control clock signal CLOCK1. This results in a change in a set-up time tS and a hold time tH of the input circuit 105. If the set-up time tS and the hold time tH change, it is difficult for the input circuit 105 to take in the signal.
 less than When Internal Output Control Clock Signal Clock2 is Affected by Noise greater than 
As shown in FIGS. 4A and 4B, if the internal output control clock signal clock2 is affected by noise, as in the case of the above-mentioned clock signal clock1, for example, the clock signal clock2 is shifted in phase with respect to the external output control clock signal CLOCK2. This causes in turn the timing for outputting a signal by the output circuit 108 to be shifted from the edge of the external output control clock signal CLOCK2. As a result, the timing for propagating the external output signal DOUT through the external signal line DQ is shifted from the edge of the external output control clock signal CLOCK2, thus resulting in a change in an output time tQ. If the output time tQ changes, for example, it is difficult for a memory controller, not shown, to take in the external output signal DOUT.
 less than When Internal Reference Potential Vref is Affected by Noise greater than 
As shown in FIGS. 5A and 5B, if the internal reference potential Vref is affected by noise, its potential fluctuates. If the internal reference potential Vref fluctuates, a difference in potential between itself and the xe2x80x9cLOWxe2x80x9d or xe2x80x9cHIGHxe2x80x9d level of an input signal decreases. Originally the internal reference potential Vref is set at an intermediate position between the xe2x80x9cLOWxe2x80x9d and xe2x80x9cHIGHxe2x80x9d levels. As such, if the potential difference between the internal reference potential Vref and the xe2x80x9cLOWxe2x80x9d or xe2x80x9cHIGHxe2x80x9d level is decreased, it is difficult for the input receiver 106 to decide the logical level.
Presently, to guard against these problems, for the set-up time tS, the hold time tH, and the output time tQ are preserved respective timing margins (hereinafter called tS margin, tH margin, and tQ margin respectively) and, for the internal reference potential Vref also are preserved voltage margins (hereinafter called VrefL margin and VrefH margin).
Taking into account ever the increasing speed and quantity of data transmitted for the synchronous semiconductor memories, however, the frequencies of the external input control clock signal CLOCK1, the internal output control clock signal CLOCK2 will be further increased highly possibly. It is, therefore, difficult to preserve the tS, tH, and tQ margins sufficiently.
Furthermore, taking into account a demand for an increase in the integration density and storage capacity of the synchronous semiconductor memories, the power supply voltage may be lowered further, in which case it is difficult also to preserve the VrefL and VrefH margins.
A semiconductor integrated circuit device according to a first aspect of the present invention comprises: a pad array including a plurality of pads; a first circuit array arranged at one side of the pad array, the first circuit array including a plurality of input receiver, a plurality of input receiver control circuits, and a plurality of output driver control circuits; a first power supply line arranged between the first circuit array and the pad array, the first power supply line being connected to the plurality of input receivers, the plurality of input receiver control circuits, and the plurality of output driver control circuits; a reference potential line arranged between the first circuit array and the pad array, the reference potential line being connected to the plurality of input receivers; an input control clock signal line arranged between the first circuit array and the pad array, the input control clock signal line being connected to the plurality of input receiver control circuits; a plurality of input signal lines arranged between the first circuit array and the pad array, the plurality of input signal lines being connected to the plurality of input receivers; an output control clock signal line arranged between the first circuit array and the pad array, the output control clock signal line being connected to the plurality of output driver control circuits; a second power supply line arranged at the other side of the pad array; and a second circuit array arranged between the second power supply line and the pad array, the second circuit array including a plurality of output drivers connected to the second power supply line.
A semiconductor device system according to a second aspect of the present invention comprises: a wiring board; and a semiconductor integrated circuit device electrically coupled to the wiring board, the wiring board including: an external signal line to which is applied an external signal; an external reference potential line to which is applied an external reference potential used to decide a logical level of the external signal; an external input control clock signal line to which is applied an external input control clock signal; and an external output control clock signal line to which is applied an external output control clock signal, the semiconductor integrated circuit device including: a pad array, the pad array including a first pad electrically coupled to the external signal line, a second pad electrically coupled to the external reference potential line, a third pad electrically coupled to the external input control clock signal line, and a fourth pad electrically coupled to the external output control clock signal line; an internal reference potential line, the internal reference potential line arranged at one side of the pad array and electrically connected to the second pad; an internal input control clock signal line, the internal input control clock signal line arranged at the one side of the pad array and electrically coupled to the third pad; an internal output control clock signal line, the internal output control clock signal line arranged at the one side of the pad array and electrically coupled to the fourth pad; an input control circuit, the input control circuit arranged at the one side of the pad array and electrically coupled to the internal input control clock signal line; an input receiver, the input receiver arranged at the one side of the pad array and electrically coupled to the input control circuit, the first pad and the internal reference potential line; an output control circuit, the output control circuit arranged at the one side of the pad array and electrically coupled to the internal output control clock signal line; a first power supply line, the first power supply line arranged at the one side of the pad array and electrically coupled to the input control circuit, the input receiver and the output control circuit; an output driver, the output driver arranged at the other side of the pad array and electrically coupled to the output control circuit and the first pad; and a second power supply line, the second power supply line arranged at the side of the pad array and electrically coupled to the output driver.